![]() Digit-serial systems, process multiple number of bits (referred to as digit-size) every clock cycle and are best suited for applications requiring moderate sample rate, where area and power consumption are critical. Bit-serial arithmetic is used for the implementation of data-flow algorithms of medium complexity and low to medium data rate, whereas bit-parallel operators may be used for the implementation of data-flow algorithms of low complexity and high data rate. Bit-serial systems are area-efficient and suitable for low-speed applications –. These systems can be synthesized using integer linear programming based scheduling approach (see Appendix F). Bit-serial systems process 1 bit of the input sample every clock cycle. Bit-parallel systems process one whole word of the input sample each clock cycle and are ideal for high-speed applications. Three implementation styles, bit-parallel, bit-serial, and digit-serial are addressed. This chapter addresses the design of bit-level architectures for addition and multiplication frequently encountered in DSP algorithms.
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